AppleSmack
Banned
EDIT: fixed error 1.
VHDL question:
2) error line 73: incompatible types for arithmetic operator: LHS=std_logic_vector!37, RHS=std_logic_vector!40
3)error line 78: incompatible types for arithmetic operator: LHS=std_logic_vector!49, RHS=std_logic_vector!52
I have no clue why 2 and 3 are errors, I'm just adding two std_logic_vectors together.
From what I remember from class you can't just add 2 logic vectors together using a standard arithmetic operator (+). You have to use a full adder port map. You should be including ieee.numeric as well. I think the reason that you can't simply add them is http://www.cs.sfu.ca/~ggbaker/reference/std_logic/arith/arith.html. According to this link VHDL can't determine wether vector is signed or unsigned unless specified.